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Renamed DataProcessing to MovShift, reducing its scope
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8d21d9c6a8
commit
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@ -9,7 +9,7 @@ set(SRCS
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ARMFuncs.cpp
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ARMFuncs.cpp
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Instructions/Instruction.cpp
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Instructions/Instruction.cpp
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Instructions/DataProcessing.cpp
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Instructions/MovShift.cpp
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Instructions/Branch.cpp
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Instructions/Branch.cpp
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)
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)
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set(HEADERS
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set(HEADERS
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@ -24,7 +24,7 @@ set(HEADERS
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Instructions/Types.h
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Instructions/Types.h
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Instructions/Instruction.h
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Instructions/Instruction.h
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Instructions/DataProcessing.h
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Instructions/MovShift.h
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Instructions/Branch.h
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Instructions/Branch.h
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)
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)
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@ -35,4 +35,4 @@ add_executable(binary_translate ${SRCS} ${HEADERS})
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target_link_libraries(binary_translate ${llvm_libs})
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target_link_libraries(binary_translate ${llvm_libs})
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target_link_libraries(binary_translate core common video_core)
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target_link_libraries(binary_translate core common video_core)
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target_link_libraries(binary_translate ${GLFW_LIBRARIES} ${OPENGL_gl_LIBRARY} inih)
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target_link_libraries(binary_translate ${GLFW_LIBRARIES} ${OPENGL_gl_LIBRARY} inih)
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target_link_libraries(binary_translate ${PLATFORM_LIBRARIES})
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target_link_libraries(binary_translate ${PLATFORM_LIBRARIES})
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@ -1,15 +1,15 @@
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#include "DataProcessing.h"
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#include "MovShift.h"
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#include "Disassembler.h"
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#include "Disassembler.h"
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#include "InstructionBlock.h"
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#include "InstructionBlock.h"
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#include "ModuleGen.h"
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#include "ModuleGen.h"
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#include "ARMFuncs.h"
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#include "ARMFuncs.h"
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static RegisterInstruction<DataProcessing> register_instruction;
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static RegisterInstruction<MovShift> register_instruction;
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bool DataProcessing::Decode()
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bool MovShift::Decode()
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{
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{
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// Mov and shifts must have zeroes at some operands of different data processing instructions
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// Mov and shifts must have zeroes at some operands of different data processing instructions
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if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>((u32)ShortOpType::MoveAndShifts), FieldDef<1>(&s), FieldDef<4>(0),
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if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>(13), FieldDef<1>(&s), FieldDef<4>(0),
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FieldDef<4>(&rd), FieldDef<5>(&imm5), FieldDef<2>(&op2), FieldDef<1>(0), FieldDef<4>(&rm) }))
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FieldDef<4>(&rd), FieldDef<5>(&imm5), FieldDef<2>(&op2), FieldDef<1>(0), FieldDef<4>(&rm) }))
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{
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{
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form = Form::Register;
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form = Form::Register;
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@ -17,17 +17,10 @@ bool DataProcessing::Decode()
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if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions;
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if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions;
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return true;
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return true;
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}
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}
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if (ReadFields({ CondDef(), FieldDef<3>(1), FieldDef<4>(&short_op), FieldDef<1>(&s), FieldDef<4>(&rn),
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FieldDef<4>(&rd), FieldDef<12>(&imm12) }))
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{
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// TODO: not implemented
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form = Form::Immediate;
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return false;
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}
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return false;
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return false;
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}
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}
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void DataProcessing::GenerateInstructionCode(InstructionBlock* instruction_block)
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void MovShift::GenerateInstructionCode(InstructionBlock* instruction_block)
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{
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{
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auto ir_builder = instruction_block->IrBuilder();
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auto ir_builder = instruction_block->IrBuilder();
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@ -6,18 +6,9 @@
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* ARMv7-A 5.2.1 (register), 5.2.2 (register-shifted register, 5.2.3 (immediate)
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* ARMv7-A 5.2.1 (register), 5.2.2 (register-shifted register, 5.2.3 (immediate)
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*/
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*/
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class DataProcessing : public Instruction
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class MovShift : public Instruction
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{
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{
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public:
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public:
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/*
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* The 4 bit op types (1 = 0001x: BitwiseXor, etc...)
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*/
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enum class ShortOpType
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{
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BitwiseAnd = 0, BitwiseXor, Subtract, RevSubtract, Add, AddWithCarry, SubtractWithCarry, ReverseSubtractWithCarry,
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// Compare, Test, Misc
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BitwiseOr = 12, MoveAndShifts, BitwiseBitClear, BitwiseNot
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};
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enum class Op2Type
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enum class Op2Type
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{
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{
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MoveAndLSL, LSR, ASR, RRXAndROR
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MoveAndLSL, LSR, ASR, RRXAndROR
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@ -32,7 +23,6 @@ public:
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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private:
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Form form;
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Form form;
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ShortOpType short_op;
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bool s;
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bool s;
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Register rn;
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Register rn;
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Register rd;
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Register rd;
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