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https://github.com/citra-emu/citra.git
synced 2024-11-24 11:21:04 +00:00
Added LDR
This commit is contained in:
parent
f8ca04f93f
commit
2839139250
@ -13,6 +13,7 @@ set(SRCS
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Instructions/MovShift.cpp
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Instructions/Branch.cpp
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Instructions/Arithmetic.cpp
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Instructions/Ldr.cpp
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)
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set(HEADERS
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CodeGen.h
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@ -30,6 +31,7 @@ set(HEADERS
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Instructions/MovShift.h
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Instructions/Branch.h
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Instructions/Arithmetic.h
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Instructions/Ldr.h
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)
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create_directory_groups(${SRCS} ${HEADERS})
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@ -49,8 +49,7 @@ public:
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* Creates a basic block for use by instructions
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*/
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llvm::BasicBlock *CreateBasicBlock(const char *name);
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/*
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/*
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* Links two instructions, adding to prev and next lists
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*/
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static void Link(InstructionBlock *prev, InstructionBlock *next);
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@ -107,5 +107,5 @@ Instruction::FieldDefObject Instruction::FieldDef(Type* field)
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template <typename Type>
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void Instruction::WriteFunction(u32 value, void *field_address)
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{
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*static_cast<Type *>(field_address) = static_cast<Type>(value);
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*static_cast<Type *>(field_address) = Type(value);
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}
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107
src/binary_translation/Instructions/Ldr.cpp
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107
src/binary_translation/Instructions/Ldr.cpp
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@ -0,0 +1,107 @@
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#include "Ldr.h"
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#include "Disassembler.h"
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#include "InstructionBlock.h"
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#include <llvm/IR/Value.h>
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#include <core/loader/loader.h>
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#include <core/mem_map.h>
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#include "MachineState.h"
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static RegisterInstruction<Ldr> register_instruction;
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bool Ldr::Decode()
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{
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if (ReadFields({ CondDef(), FieldDef<4>(5), FieldDef<1>(&U), FieldDef<7>(0x1f),
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FieldDef<4>(&rt), FieldDef<12>(&imm12)}))
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{
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form = Form::PC;
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return true;
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}
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if (ReadFields({ CondDef(), FieldDef<3>(2), FieldDef<1>(&P), FieldDef<1>(&U), FieldDef<1>(0), FieldDef<1>(&W), FieldDef<1>(1), FieldDef<4>(&rn),
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FieldDef<4>(&rt), FieldDef<12>(&imm12) }))
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{
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form = Form::Reg;
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if (!P && W) return false; // SEE LDRT;
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if (rn == Register::SP && !P && U && !W && imm12 == 4) return false; // SEE POP;
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if ((!P || W) && rn == rt) return false; // UNPREDICTABLE;
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return true;
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}
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if (ReadFields({ CondDef(), FieldDef<6>(0x22), FieldDef<1>(&W), FieldDef<1>(1), FieldDef<4>(&rn),
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FieldDef<16>(®ister_list) }))
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{
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form = Form::MultiReg;
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if (W && rn == Register::SP && register_list.size() > 1) return false; // SEE POP (ARM);
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if (rn == Register::PC || register_list.size() < 1) return false; // UNPREDICTABLE;
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if (W && register_list[(u32)rn]) return false; // UNPREDICTABLE;
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return true;
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}
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return false;
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}
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void Ldr::GenerateInstructionCode(InstructionBlock* instruction_block)
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{
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auto ir_builder = instruction_block->IrBuilder();
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if (form != Form::MultiReg)
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{
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llvm::Value *address = nullptr;
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llvm::Value *value = nullptr;
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auto add = (bool)U;
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if (form == Form::PC)
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{
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auto base = instruction_block->Address() + 8;
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auto constAddress = add ? base + imm12 : base - imm12;
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auto constAddressEnd = constAddress + 4;
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// If the value is read only, inline it
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if (constAddress >= Loader::ROMCodeStart && constAddressEnd <= (Loader::ROMCodeStart + Loader::ROMCodeSize) ||
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constAddress >= Loader::ROMReadOnlyDataStart && constAddressEnd <= (Loader::ROMReadOnlyDataStart + Loader::ROMReadOnlyDataSize))
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{
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value = ir_builder->getInt32(Memory::Read32(constAddress));
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}
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else
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{
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address = ir_builder->getInt32(constAddress);
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}
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}
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else
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{
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auto index = (bool)P;
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auto wback = !P || W;
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auto source_register = instruction_block->Read(rn);
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auto imm32 = ir_builder->getInt32(add ? imm12 : -imm12);
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auto offset_address = ir_builder->CreateAdd(source_register, imm32);
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address = index ? offset_address : source_register;
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if (wback)
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instruction_block->Write(rn, offset_address);
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}
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if (!value) value = instruction_block->Module()->Machine()->ReadMemory32(address);
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instruction_block->Write(rt, value);
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if (rt == Register::PC)
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instruction_block->Module()->BranchReadPC();
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}
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else
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{
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auto wback = (bool)W;
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auto address = instruction_block->Read(rn);
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for (auto i = 0; i < 16; ++i)
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{
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if (!register_list[i]) continue;
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instruction_block->Write((Register)i, instruction_block->Module()->Machine()->ReadMemory32(address));
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address = ir_builder->CreateAdd(address, ir_builder->getInt32(4));
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}
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if (wback)
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instruction_block->Write(rn, address);
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if (register_list[15])
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instruction_block->Module()->BranchReadPC();
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}
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}
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26
src/binary_translation/Instructions/Ldr.h
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26
src/binary_translation/Instructions/Ldr.h
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@ -0,0 +1,26 @@
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#include "Instruction.h"
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#include "Types.h"
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#include <bitset>
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class Ldr : public Instruction
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{
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public:
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enum class Form
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{
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PC, Reg, MultiReg
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};
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public:
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virtual bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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Form form;
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bool U;
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Register rt;
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u32 imm12;
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bool P;
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bool W;
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Register rn;
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std::bitset<16> register_list;
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};
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@ -23,6 +23,12 @@ void MachineState::GenerateGlobals()
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auto flags_global_initializer = ConstantPointerNull::get(IntegerType::getInt1PtrTy(getGlobalContext()));
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flags_global = new GlobalVariable(*module->Module(), flags_global_initializer->getType(),
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false, GlobalValue::ExternalLinkage, flags_global_initializer, "Flags");
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auto memory_read_32_signature = FunctionType::get(IntegerType::getInt32Ty(getGlobalContext()), IntegerType::getInt32Ty(getGlobalContext()), false);
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auto memory_read_32_ptr = PointerType::get(memory_read_32_signature, 0);
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auto memory_read_32_initializer = ConstantPointerNull::get(memory_read_32_ptr);
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memory_read_32_global = new GlobalVariable(*module->Module(), memory_read_32_ptr,
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false, GlobalValue::ExternalLinkage, memory_read_32_initializer, "Memory::Read32");
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}
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Value *MachineState::GetRegisterPtr(Register reg)
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@ -87,4 +93,17 @@ Value* MachineState::ConditionPassed(Condition cond)
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if (not) pred = ir_builder->CreateNot(pred);
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return pred;
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}
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llvm::Value* MachineState::ReadMemory32(llvm::Value* address)
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{
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auto ir_builder = module->IrBuilder();
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auto memory_read_32 = ir_builder->CreateLoad(memory_read_32_global);
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module->GetTBAA()->TagConst(memory_read_32);
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auto call = ir_builder->CreateCall(memory_read_32, address);
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call->setOnlyReadsMemory();
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module->GetTBAA()->TagMemory(call);
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return call;
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}
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@ -23,6 +23,7 @@ public:
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llvm::Value *ReadRegiser(Register reg);
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llvm::Value *WriteRegiser(Register reg, llvm::Value *value);
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llvm::Value* ConditionPassed(Condition cond);
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llvm::Value* ReadMemory32(llvm::Value* address);
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private:
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// Returns the address of a register or a flag
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llvm::Value *GetRegisterPtr(Register reg);
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@ -40,4 +41,10 @@ private:
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* Orderered N, Z, C, V
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*/
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llvm::GlobalVariable *flags_global;
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/*
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* u32 (u32) Memory::Read
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* Reads the memory at address
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*/
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llvm::GlobalVariable *memory_read_32_global;
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};
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@ -21,6 +21,7 @@ void TBAA::GenerateTags()
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}
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const_node = md_builder.createTBAAScalarTypeNode("Readonly", tbaa_root);
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instruction_count_node = md_builder.createTBAAScalarTypeNode("InstructionCount", tbaa_root);
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memory_node = md_builder.createTBAAScalarTypeNode("Memory", tbaa_root);
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}
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void TBAA::TagRegister(Instruction* instruction, Register reg)
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@ -36,4 +37,9 @@ void TBAA::TagConst(Instruction* instruction)
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void TBAA::TagInstructionCount(llvm::Instruction* instruction)
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{
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instruction->setMetadata(LLVMContext::MD_tbaa, instruction_count_node);
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}
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void TBAA::TagMemory(llvm::Instruction* instruction)
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{
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instruction->setMetadata(LLVMContext::MD_tbaa, memory_node);
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}
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@ -1,5 +1,6 @@
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#pragma once
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#include "Instructions/Types.h"
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#include <llvm/IR/Instructions.h>
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namespace llvm
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{
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@ -22,10 +23,12 @@ public:
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void TagRegister(llvm::Instruction *instruction, Register reg);
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void TagConst(llvm::Instruction *instruction);
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void TagInstructionCount(llvm::Instruction *instruction);
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void TagMemory(llvm::Instruction *instruction);
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private:
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llvm::MDNode *register_nodes[RegisterCount];
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// Tag for everything that is never written.
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// Since it is never written, one tag works
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llvm::MDNode *const_node;
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llvm::MDNode *instruction_count_node;
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llvm::MDNode *memory_node;
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};
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@ -6,6 +6,7 @@
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#include <llvm/Object/ObjectFile.h>
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#include <llvm/ExecutionEngine/RuntimeDyld.h>
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#include <llvm/ExecutionEngine/SectionMemoryManager.h>
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#include <core/mem_map.h>
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using namespace llvm;
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@ -120,14 +121,16 @@ void BinaryTranslationLoader::Load(FileUtil::IOFile& file)
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g_can_run_function = static_cast<decltype(g_can_run_function)>(g_dyld->getSymbolAddress("CanRun"));
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auto verify_ptr = static_cast<bool*>(g_dyld->getSymbolAddress("Verify"));
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g_instruction_count = static_cast<uint32_t *>(g_dyld->getSymbolAddress("InstructionCount"));
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auto memory_read_32_ptr = static_cast<decltype(&Memory::Read32) *>(g_dyld->getSymbolAddress("Memory::Read32"));
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if (!g_run_function || !g_can_run_function || !verify_ptr || !g_instruction_count)
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if (!g_run_function || !g_can_run_function || !verify_ptr || !g_instruction_count || !memory_read_32_ptr)
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{
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LOG_WARNING(Loader, "Cannot load optimized file, missing critical function");
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return;
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}
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g_verify = *verify_ptr;
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*memory_read_32_ptr = &Memory::Read32;
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g_enabled = true;
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