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https://github.com/citra-emu/citra.git
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tests/JitX64: Fuzz ARM data processing instructions
This commit is contained in:
MerryMage
parent
91152ad2b2
commit
02c3484dbc
@ -24,14 +24,14 @@ static JitState* CallInterpreter(JitState* jit_state, u64 pc, u64 TFlag, u64 EFl
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(cpu->VFlag << 28) |
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(cpu->TFlag << 5);
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if (jit_state->cycles_remaining > 0) {
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if (jit_state->cycles_remaining >= 0) {
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#if 0
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cpu->NumInstrsToExecute = jit_state->cycles_remaining;
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cpu->NumInstrsToExecute = jit_state->cycles_remaining + 1;
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if (cpu->NumInstrsToExecute > 100) cpu->NumInstrsToExecute = 100;
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jit_state->cycles_remaining -= InterpreterMainLoop(cpu);
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jit_state->cycles_remaining -= InterpreterMainLoop(cpu) - 1;
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#else
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cpu->NumInstrsToExecute = 1;
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jit_state->cycles_remaining -= InterpreterMainLoop(cpu);
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jit_state->cycles_remaining -= InterpreterMainLoop(cpu) - 1;
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#endif
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}
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@ -67,6 +67,7 @@ void JitX64::CompileInterpretInstruction() {
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// Return to dispatch
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code->JMPptr(MJitStateHostReturnRIP());
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current.arm_pc += GetInstSize();
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stop_compilation = true;
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}
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@ -7,6 +7,7 @@
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#include "common/common_types.h"
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#include "core/memory.h"
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#include "core/mmio.h"
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namespace Memory {
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@ -5,6 +5,12 @@ set(SRCS
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set(HEADERS
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)
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if(ARCHITECTURE_x86_64)
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set(SRCS ${SRCS}
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core/arm/jit_x64/fuzz_arm_data_processing.cpp
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)
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endif()
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create_directory_groups(${SRCS} ${HEADERS})
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include_directories(../../externals/catch)
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201
src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp
Normal file
201
src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp
Normal file
@ -0,0 +1,201 @@
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// Copyright 2016 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <random>
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#include <catch.hpp>
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#include "common/common_types.h"
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#include "common/scope_exit.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/dyncom/arm_dyncom.h"
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#include "core/arm/jit_x64/interface.h"
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#include "core/core.h"
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#include "core/memory_setup.h"
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std::pair<u32, u32> FromBitString(const char* str) {
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REQUIRE(strlen(str) == 32);
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u32 bits = 0;
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u32 mask = 0;
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for (int i = 0; i < 32; i++) {
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const u32 bit = 1 << (31 - i);
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switch (str[i]) {
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case '0':
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mask |= bit;
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break;
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case '1':
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bits |= bit;
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mask |= bit;
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break;
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default:
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// Do nothing
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break;
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}
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}
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return { bits, mask };
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}
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TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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// Init core
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Core::Init();
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SCOPE_EXIT({ Core::Shutdown(); });
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// Prepare random numbers
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std::random_device rd;
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std::mt19937 mt(rd());
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auto rand_int = [&mt](u32 min, u32 max) -> u32 {
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std::uniform_int<u32> rand(min, max);
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return rand(mt);
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};
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// Prepare memory
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u8* test_mem = new u8[4096 * 2];
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std::memset(test_mem, 0, 4096 * 2);
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Memory::MapMemoryRegion(0, 4096 * 2, test_mem);
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SCOPE_EXIT({ Memory::UnmapRegion(0, 4096 * 2); });
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// Prepare test subjects
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JitX64::ARM_Jit jit(PrivilegeMode::USER32MODE);
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ARM_DynCom interp(PrivilegeMode::USER32MODE);
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SCOPE_EXIT({
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jit.ClearCache();
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interp.ClearCache();
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});
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for (int run_number = 0; run_number < 10000; run_number++) {
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jit.ClearCache();
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interp.ClearCache();
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u32 initial_regs[15];
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for (int i = 0; i < 15; i++) {
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u32 val = rand_int(0, 0xFFFFFFFF);
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interp.SetReg(i, val);
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jit.SetReg(i, val);
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initial_regs[i] = val;
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}
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interp.SetCPSR(0x000001d0);
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jit.SetCPSR(0x000001d0);
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interp.SetPC(0);
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jit.SetPC(0);
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constexpr int NUM_INST = 5;
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for (int i = 0; i < NUM_INST; i++) {
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const std::array<std::pair<u32, u32>, 48> instructions = {{
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FromBitString("cccc0010101Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000101Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000101Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010100Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000100Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000100Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010000Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000000Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000000Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0011110Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0001110Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0001110Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc00110111nnnn0000rrrrvvvvvvvv"),
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FromBitString("cccc00010111nnnn0000vvvvvrr0mmmm"),
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FromBitString("cccc00010111nnnn0000ssss0rr1mmmm"),
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FromBitString("cccc00110101nnnn0000rrrrvvvvvvvv"),
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FromBitString("cccc00010101nnnn0000vvvvvrr0mmmm"),
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FromBitString("cccc00010101nnnn0000ssss0rr1mmmm"),
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FromBitString("cccc0010001Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000001Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000001Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0011101S0000ddddrrrrvvvvvvvv"),
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FromBitString("cccc0001101S0000ddddvvvvvrr0mmmm"),
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FromBitString("cccc0001101S0000ddddssss0rr1mmmm"),
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FromBitString("cccc0011111S0000ddddrrrrvvvvvvvv"),
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FromBitString("cccc0001111S0000ddddvvvvvrr0mmmm"),
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FromBitString("cccc0001111S0000ddddssss0rr1mmmm"),
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FromBitString("cccc0011100Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0001100Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0001100Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010011Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000011Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000011Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010111Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000111Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000111Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010110Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000110Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000110Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc0010010Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0000010Snnnnddddvvvvvrr0mmmm"),
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FromBitString("cccc0000010Snnnnddddssss0rr1mmmm"),
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FromBitString("cccc00110011nnnn0000rrrrvvvvvvvv"),
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FromBitString("cccc00010011nnnn0000vvvvvrr0mmmm"),
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FromBitString("cccc00010011nnnn0000ssss0rr1mmmm"),
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FromBitString("cccc00110001nnnn0000rrrrvvvvvvvv"),
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FromBitString("cccc00010001nnnn0000vvvvvrr0mmmm"),
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FromBitString("cccc00010001nnnn0000ssss0rr1mmmm"),
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}};
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size_t inst_index = rand_int(0, instructions.size() - 1);
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u32 cond = rand_int(0x0, 0xE);
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u32 Rn = rand_int(0, 15);
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u32 Rd = rand_int(0, 14);
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u32 S = rand_int(0, 1);
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u32 shifter_operand = rand_int(0, 0xFFF);
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u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28);
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u32 inst = instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second));
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Memory::Write32(i * 4, inst);
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}
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Memory::Write32(NUM_INST * 4, 0b11100011001000000000111100000000);
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interp.ExecuteInstructions(NUM_INST);
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jit.ExecuteInstructions(NUM_INST);
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bool pass = true;
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if (interp.GetCPSR() != jit.GetCPSR()) pass = false;
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for (int i = 0; i <= 15; i++) {
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if (interp.GetReg(i) != jit.GetReg(i)) pass = false;
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}
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if (!pass) {
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printf("Failed at execution number %i\n", run_number);
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printf("\nInstruction Listing: \n");
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for (int i = 0; i < NUM_INST; i++) {
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printf("%s\n", ARM_Disasm::Disassemble(i * 4, Memory::Read32(i * 4)).c_str());
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}
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printf("\nFinal Register Listing: \n");
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x %08x %s\n", i, interp.GetReg(i), jit.GetReg(i), interp.GetReg(i) != jit.GetReg(i) ? "*" : "");
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}
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printf("CPSR: %08x %08x %s\n", interp.GetCPSR(), jit.GetCPSR(), interp.GetCPSR() != jit.GetCPSR() ? "*" : "");
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printf("\nInterpreter walkthrough:\n");
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interp.ClearCache();
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interp.SetPC(0);
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interp.SetCPSR(0x000001d0);
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for (int i = 0; i < 15; i++) {
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interp.SetReg(i, initial_regs[i]);
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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for (int inst = 0; inst < NUM_INST; inst++) {
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printf("%s\n", ARM_Disasm::Disassemble(inst * 4, Memory::Read32(inst * 4)).c_str());
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interp.Step();
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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printf("CPSR: %08x\n", interp.GetCPSR());
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}
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FAIL();
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}
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}
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}
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