2015-05-13 01:38:29 +00:00
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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2016-11-24 19:42:32 +00:00
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#include <array>
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2015-06-21 12:12:49 +00:00
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#include <cstddef>
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2018-12-01 22:46:18 +00:00
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#include <memory>
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2016-06-27 17:42:42 +00:00
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#include <string>
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2017-07-22 02:17:57 +00:00
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#include <vector>
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2020-01-03 17:19:59 +00:00
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#include <boost/serialization/array.hpp>
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#include <boost/serialization/vector.hpp>
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2015-05-13 01:38:29 +00:00
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#include "common/common_types.h"
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2020-01-04 22:39:54 +00:00
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#include "common/memory_ref.h"
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2017-07-22 02:17:57 +00:00
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#include "core/mmio.h"
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2015-05-13 01:38:29 +00:00
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2019-02-01 17:43:55 +00:00
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class ARM_Interface;
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2017-09-26 22:27:44 +00:00
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namespace Kernel {
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class Process;
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}
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2019-02-04 02:33:20 +00:00
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namespace AudioCore {
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class DspInterface;
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}
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2015-05-13 01:38:29 +00:00
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namespace Memory {
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2018-11-19 02:01:11 +00:00
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// Are defined in a system header
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#undef PAGE_SIZE
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#undef PAGE_MASK
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2015-05-13 02:38:56 +00:00
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/**
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* Page size used by the ARM architecture. This is the smallest granularity with which memory can
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* be mapped.
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*/
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2015-05-13 01:38:29 +00:00
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const u32 PAGE_SIZE = 0x1000;
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2015-07-19 05:22:28 +00:00
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const u32 PAGE_MASK = PAGE_SIZE - 1;
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const int PAGE_BITS = 12;
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2018-09-06 20:03:28 +00:00
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const std::size_t PAGE_TABLE_NUM_ENTRIES = 1 << (32 - PAGE_BITS);
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2015-05-13 01:38:29 +00:00
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2017-07-22 02:17:57 +00:00
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enum class PageType {
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/// Page is unmapped and should cause an access error.
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Unmapped,
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/// Page is mapped to regular memory. This is the only type you can get pointers to.
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Memory,
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/// Page is mapped to regular memory, but also needs to check for rasterizer cache flushing and
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/// invalidation
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RasterizerCachedMemory,
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/// Page is mapped to a I/O region. Writing and reading to this page is handled by functions.
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Special,
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};
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struct SpecialRegion {
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VAddr base;
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u32 size;
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MMIORegionPointer handler;
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2019-08-06 14:59:31 +00:00
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2020-01-03 17:19:59 +00:00
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private:
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2019-12-27 21:07:29 +00:00
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template <class Archive>
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void serialize(Archive& ar, const unsigned int file_version) {
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ar& base;
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ar& size;
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ar& handler;
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2019-08-06 14:59:31 +00:00
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}
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2020-01-03 17:19:59 +00:00
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friend class boost::serialization::access;
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2017-07-22 02:17:57 +00:00
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};
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/**
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* A (reasonably) fast way of allowing switchable and remappable process address spaces. It loosely
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* mimics the way a real CPU page table works, but instead is optimized for minimal decoding and
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* fetching requirements when accessing. In the usual case of an access to regular memory, it only
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* requires an indexed fetch and a check for NULL.
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*/
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struct PageTable {
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/**
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* Array of memory pointers backing each page. An entry can only be non-null if the
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* corresponding entry in the `attributes` array is of type `Memory`.
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*/
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2020-01-04 22:39:54 +00:00
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// The reason for this rigmarole is to keep the 'raw' and 'refs' arrays in sync.
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// We need 'raw' for dynarmic and 'refs' for serialization
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struct Pointers {
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struct Entry {
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Entry(Pointers& pointers_, VAddr idx_) : pointers(pointers_), idx(idx_) {}
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2020-03-31 16:54:28 +00:00
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void operator=(MemoryRef value) {
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2020-01-04 22:39:54 +00:00
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pointers.refs[idx] = value;
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pointers.raw[idx] = value.GetPtr();
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}
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2020-03-31 16:54:28 +00:00
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operator u8*() {
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2020-01-04 22:39:54 +00:00
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return pointers.raw[idx];
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}
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private:
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Pointers& pointers;
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VAddr idx;
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};
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2020-03-31 16:54:28 +00:00
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Entry operator[](VAddr idx) {
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2020-01-04 22:39:54 +00:00
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return Entry(*this, idx);
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}
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2020-03-31 16:54:28 +00:00
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u8* operator[](VAddr idx) const {
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2020-01-04 22:39:54 +00:00
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return raw[idx];
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}
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2020-03-31 16:54:28 +00:00
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Entry operator[](std::size_t idx) {
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2020-01-04 22:39:54 +00:00
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return Entry(*this, static_cast<VAddr>(idx));
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}
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private:
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std::array<u8*, PAGE_TABLE_NUM_ENTRIES> raw;
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std::array<MemoryRef, PAGE_TABLE_NUM_ENTRIES> refs;
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friend struct PageTable;
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};
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Pointers pointers;
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2017-07-22 02:17:57 +00:00
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/**
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* Contains MMIO handlers that back memory regions whose entries in the `attribute` array is of
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* type `Special`.
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*/
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std::vector<SpecialRegion> special_regions;
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/**
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* Array of fine grained page attributes. If it is set to any value other than `Memory`, then
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* the corresponding entry in `pointers` MUST be set to null.
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*/
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std::array<PageType, PAGE_TABLE_NUM_ENTRIES> attributes;
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2020-01-03 17:19:59 +00:00
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2020-03-31 16:54:28 +00:00
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std::array<u8*, PAGE_TABLE_NUM_ENTRIES>& GetPointerArray() {
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2020-01-04 22:39:54 +00:00
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return pointers.raw;
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}
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void Clear();
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2020-01-03 17:19:59 +00:00
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private:
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template <class Archive>
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void serialize(Archive& ar, const unsigned int) {
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2020-01-04 22:39:54 +00:00
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ar& pointers.refs;
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2020-01-03 17:19:59 +00:00
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ar& special_regions;
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ar& attributes;
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2020-01-04 22:39:54 +00:00
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for (auto i = 0; i < PAGE_TABLE_NUM_ENTRIES; i++) {
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pointers.raw[i] = pointers.refs[i].GetPtr();
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}
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2020-01-03 17:19:59 +00:00
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}
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friend class boost::serialization::access;
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2017-07-22 02:17:57 +00:00
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};
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2015-05-13 01:38:29 +00:00
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/// Physical memory regions as seen from the ARM11
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enum : PAddr {
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/// IO register area
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2016-09-18 00:38:01 +00:00
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IO_AREA_PADDR = 0x10100000,
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2018-11-12 20:12:12 +00:00
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IO_AREA_SIZE = 0x00400000, ///< IO area size (4MB)
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2015-05-13 01:38:29 +00:00
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IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
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/// MPCore internal memory region
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2016-09-18 00:38:01 +00:00
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MPCORE_RAM_PADDR = 0x17E00000,
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MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
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2015-05-13 01:38:29 +00:00
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MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
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/// Video memory
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2016-09-18 00:38:01 +00:00
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VRAM_PADDR = 0x18000000,
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VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
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2015-05-13 01:38:29 +00:00
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VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
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2017-05-01 00:13:53 +00:00
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/// New 3DS additional memory. Supposedly faster than regular FCRAM. Part of it can be used by
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/// applications and system modules if mapped via the ExHeader.
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N3DS_EXTRA_RAM_PADDR = 0x1F000000,
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N3DS_EXTRA_RAM_SIZE = 0x00400000, ///< New 3DS additional memory size (4MB)
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N3DS_EXTRA_RAM_PADDR_END = N3DS_EXTRA_RAM_PADDR + N3DS_EXTRA_RAM_SIZE,
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2015-05-13 01:38:29 +00:00
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/// DSP memory
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2016-09-18 00:38:01 +00:00
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DSP_RAM_PADDR = 0x1FF00000,
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DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
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2015-05-13 01:38:29 +00:00
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DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
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/// AXI WRAM
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2016-09-18 00:38:01 +00:00
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AXI_WRAM_PADDR = 0x1FF80000,
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AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
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2015-05-13 01:38:29 +00:00
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AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
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/// Main FCRAM
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2016-09-18 00:38:01 +00:00
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FCRAM_PADDR = 0x20000000,
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2017-06-19 01:39:17 +00:00
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FCRAM_SIZE = 0x08000000, ///< FCRAM size on the Old 3DS (128MB)
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FCRAM_N3DS_SIZE = 0x10000000, ///< FCRAM size on the New 3DS (256MB)
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2015-05-13 01:38:29 +00:00
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FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
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2017-06-19 01:39:17 +00:00
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FCRAM_N3DS_PADDR_END = FCRAM_PADDR + FCRAM_N3DS_SIZE,
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2015-05-13 01:38:29 +00:00
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};
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2020-01-04 22:39:54 +00:00
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enum class Region { FCRAM, VRAM, DSP, N3DS };
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2015-05-13 01:38:29 +00:00
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/// Virtual user-space memory regions
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enum : VAddr {
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/// Where the application text, data and bss reside.
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2016-09-18 00:38:01 +00:00
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PROCESS_IMAGE_VADDR = 0x00100000,
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PROCESS_IMAGE_MAX_SIZE = 0x03F00000,
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2015-05-13 01:38:29 +00:00
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PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
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/// Area where IPC buffers are mapped onto.
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2016-09-18 00:38:01 +00:00
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IPC_MAPPING_VADDR = 0x04000000,
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IPC_MAPPING_SIZE = 0x04000000,
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2015-05-13 01:38:29 +00:00
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IPC_MAPPING_VADDR_END = IPC_MAPPING_VADDR + IPC_MAPPING_SIZE,
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/// Application heap (includes stack).
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2016-09-18 00:38:01 +00:00
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HEAP_VADDR = 0x08000000,
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HEAP_SIZE = 0x08000000,
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2015-05-13 01:38:29 +00:00
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HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
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/// Area where shared memory buffers are mapped onto.
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2016-09-18 00:38:01 +00:00
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SHARED_MEMORY_VADDR = 0x10000000,
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SHARED_MEMORY_SIZE = 0x04000000,
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2015-05-13 01:38:29 +00:00
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SHARED_MEMORY_VADDR_END = SHARED_MEMORY_VADDR + SHARED_MEMORY_SIZE,
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2016-09-18 00:38:01 +00:00
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/// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical
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/// memory.
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LINEAR_HEAP_VADDR = 0x14000000,
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LINEAR_HEAP_SIZE = 0x08000000,
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2015-05-13 01:38:29 +00:00
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LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
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2017-05-01 00:13:53 +00:00
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/// Maps 1:1 to New 3DS additional memory
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N3DS_EXTRA_RAM_VADDR = 0x1E800000,
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N3DS_EXTRA_RAM_VADDR_END = N3DS_EXTRA_RAM_VADDR + N3DS_EXTRA_RAM_SIZE,
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2015-05-13 01:38:29 +00:00
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/// Maps 1:1 to the IO register area.
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2016-09-18 00:38:01 +00:00
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IO_AREA_VADDR = 0x1EC00000,
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2015-05-13 01:38:29 +00:00
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IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
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/// Maps 1:1 to VRAM.
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2016-09-18 00:38:01 +00:00
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VRAM_VADDR = 0x1F000000,
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2015-05-13 01:38:29 +00:00
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VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
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/// Maps 1:1 to DSP memory.
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2016-09-18 00:38:01 +00:00
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DSP_RAM_VADDR = 0x1FF00000,
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2015-05-13 01:38:29 +00:00
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DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
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/// Read-only page containing kernel and system configuration values.
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2016-09-18 00:38:01 +00:00
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CONFIG_MEMORY_VADDR = 0x1FF80000,
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CONFIG_MEMORY_SIZE = 0x00001000,
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2015-05-13 01:38:29 +00:00
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CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
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/// Usually read-only page containing mostly values read from hardware.
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2016-09-18 00:38:01 +00:00
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SHARED_PAGE_VADDR = 0x1FF81000,
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SHARED_PAGE_SIZE = 0x00001000,
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2015-05-13 01:38:29 +00:00
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SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
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/// Area where TLS (Thread-Local Storage) buffers are allocated.
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2016-09-18 00:38:01 +00:00
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TLS_AREA_VADDR = 0x1FF82000,
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TLS_ENTRY_SIZE = 0x200,
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2015-08-06 00:39:53 +00:00
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2015-08-06 00:26:52 +00:00
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/// Equivalent to LINEAR_HEAP_VADDR, but expanded to cover the extra memory in the New 3DS.
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2016-09-18 00:38:01 +00:00
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NEW_LINEAR_HEAP_VADDR = 0x30000000,
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NEW_LINEAR_HEAP_SIZE = 0x10000000,
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2015-08-06 00:26:52 +00:00
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NEW_LINEAR_HEAP_VADDR_END = NEW_LINEAR_HEAP_VADDR + NEW_LINEAR_HEAP_SIZE,
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2015-05-13 01:38:29 +00:00
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};
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2016-04-16 22:57:57 +00:00
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/**
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* Flushes any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushRegion(PAddr start, u32 size);
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2017-11-23 17:43:12 +00:00
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/**
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* Invalidates any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerInvalidateRegion(PAddr start, u32 size);
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2016-04-16 22:57:57 +00:00
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/**
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* Flushes and invalidates any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushAndInvalidateRegion(PAddr start, u32 size);
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2016-11-24 19:42:32 +00:00
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2017-06-22 05:48:00 +00:00
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enum class FlushMode {
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/// Write back modified surfaces to RAM
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Flush,
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2017-11-23 17:43:12 +00:00
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/// Remove region from the cache
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Invalidate,
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2017-06-22 05:48:00 +00:00
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/// Write back modified surfaces to RAM, and also remove them from the cache
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FlushAndInvalidate,
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};
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2020-01-17 06:17:55 +00:00
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/**
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* Flushes and invalidates all memory in the rasterizer cache and removes any leftover state
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* If flush is true, the rasterizer should flush any cached resources to RAM before clearing
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|
*/
|
|
|
|
void RasterizerClearAll(bool flush);
|
|
|
|
|
2017-06-22 05:48:00 +00:00
|
|
|
/**
|
|
|
|
* Flushes and invalidates any externally cached rasterizer resources touching the given virtual
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|
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|
* address region.
|
|
|
|
*/
|
|
|
|
void RasterizerFlushVirtualRegion(VAddr start, u32 size, FlushMode mode);
|
|
|
|
|
2018-11-21 03:38:47 +00:00
|
|
|
class MemorySystem {
|
2018-11-21 03:52:44 +00:00
|
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|
public:
|
2018-12-01 22:46:18 +00:00
|
|
|
MemorySystem();
|
|
|
|
~MemorySystem();
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|
|
|
|
2018-12-11 03:01:09 +00:00
|
|
|
/**
|
|
|
|
* Maps an allocated buffer onto a region of the emulated process address space.
|
|
|
|
*
|
|
|
|
* @param page_table The page table of the emulated process.
|
|
|
|
* @param base The address to start mapping at. Must be page-aligned.
|
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|
|
* @param size The amount of bytes to map. Must be page-aligned.
|
|
|
|
* @param target Buffer with the memory backing the mapping. Must be of length at least `size`.
|
|
|
|
*/
|
2020-01-04 22:39:54 +00:00
|
|
|
void MapMemoryRegion(PageTable& page_table, VAddr base, u32 size, MemoryRef target);
|
2018-12-11 03:01:09 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Maps a region of the emulated process address space as a IO region.
|
|
|
|
* @param page_table The page table of the emulated process.
|
|
|
|
* @param base The address to start mapping at. Must be page-aligned.
|
|
|
|
* @param size The amount of bytes to map. Must be page-aligned.
|
|
|
|
* @param mmio_handler The handler that backs the mapping.
|
|
|
|
*/
|
|
|
|
void MapIoRegion(PageTable& page_table, VAddr base, u32 size, MMIORegionPointer mmio_handler);
|
|
|
|
|
|
|
|
void UnmapRegion(PageTable& page_table, VAddr base, u32 size);
|
|
|
|
|
2018-11-21 04:50:00 +00:00
|
|
|
/// Currently active page table
|
2020-01-05 16:35:01 +00:00
|
|
|
void SetCurrentPageTable(std::shared_ptr<PageTable> page_table);
|
|
|
|
std::shared_ptr<PageTable> GetCurrentPageTable() const;
|
2018-11-21 04:50:00 +00:00
|
|
|
|
2018-11-21 20:04:31 +00:00
|
|
|
u8 Read8(VAddr addr);
|
|
|
|
u16 Read16(VAddr addr);
|
|
|
|
u32 Read32(VAddr addr);
|
|
|
|
u64 Read64(VAddr addr);
|
|
|
|
|
|
|
|
void Write8(VAddr addr, u8 data);
|
|
|
|
void Write16(VAddr addr, u16 data);
|
|
|
|
void Write32(VAddr addr, u32 data);
|
|
|
|
void Write64(VAddr addr, u64 data);
|
|
|
|
|
2018-11-21 20:21:30 +00:00
|
|
|
void ReadBlock(const Kernel::Process& process, VAddr src_addr, void* dest_buffer,
|
|
|
|
std::size_t size);
|
|
|
|
void WriteBlock(const Kernel::Process& process, VAddr dest_addr, const void* src_buffer,
|
|
|
|
std::size_t size);
|
|
|
|
void ZeroBlock(const Kernel::Process& process, VAddr dest_addr, const std::size_t size);
|
|
|
|
void CopyBlock(const Kernel::Process& process, VAddr dest_addr, VAddr src_addr,
|
|
|
|
std::size_t size);
|
2019-04-19 18:15:05 +00:00
|
|
|
void CopyBlock(const Kernel::Process& dest_process, const Kernel::Process& src_process,
|
|
|
|
VAddr dest_addr, VAddr src_addr, std::size_t size);
|
2018-11-21 20:21:30 +00:00
|
|
|
|
2018-11-21 20:04:31 +00:00
|
|
|
std::string ReadCString(VAddr vaddr, std::size_t max_length);
|
|
|
|
|
2018-11-21 17:01:19 +00:00
|
|
|
/**
|
|
|
|
* Gets a pointer to the memory region beginning at the specified physical address.
|
|
|
|
*/
|
|
|
|
u8* GetPhysicalPointer(PAddr address);
|
|
|
|
|
2020-01-04 22:39:54 +00:00
|
|
|
MemoryRef GetPhysicalRef(PAddr address);
|
|
|
|
|
2018-11-21 18:51:12 +00:00
|
|
|
u8* GetPointer(VAddr vaddr);
|
|
|
|
|
2018-11-21 17:01:19 +00:00
|
|
|
bool IsValidPhysicalAddress(PAddr paddr);
|
|
|
|
|
2018-11-21 03:52:44 +00:00
|
|
|
/// Gets offset in FCRAM from a pointer inside FCRAM range
|
2020-01-04 22:39:54 +00:00
|
|
|
u32 GetFCRAMOffset(const u8* pointer);
|
2018-11-21 20:04:31 +00:00
|
|
|
|
2018-12-01 22:46:18 +00:00
|
|
|
/// Gets pointer in FCRAM with given offset
|
|
|
|
u8* GetFCRAMPointer(u32 offset);
|
|
|
|
|
2020-01-04 22:39:54 +00:00
|
|
|
/// Gets a serializable ref to FCRAM with the given offset
|
|
|
|
MemoryRef GetFCRAMRef(u32 offset);
|
|
|
|
|
2018-11-21 21:03:28 +00:00
|
|
|
/**
|
|
|
|
* Mark each page touching the region as cached.
|
|
|
|
*/
|
|
|
|
void RasterizerMarkRegionCached(PAddr start, u32 size, bool cached);
|
|
|
|
|
2018-12-11 03:13:10 +00:00
|
|
|
/// Registers page table for rasterizer cache marking
|
2020-01-05 16:35:01 +00:00
|
|
|
void RegisterPageTable(std::shared_ptr<PageTable> page_table);
|
2018-12-11 03:13:10 +00:00
|
|
|
|
|
|
|
/// Unregisters page table for rasterizer cache marking
|
2020-01-05 16:35:01 +00:00
|
|
|
void UnregisterPageTable(std::shared_ptr<PageTable> page_table);
|
2018-12-11 03:13:10 +00:00
|
|
|
|
2019-02-04 02:33:20 +00:00
|
|
|
void SetDSP(AudioCore::DspInterface& dsp);
|
|
|
|
|
2018-11-21 20:04:31 +00:00
|
|
|
private:
|
|
|
|
template <typename T>
|
|
|
|
T Read(const VAddr vaddr);
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
void Write(const VAddr vaddr, const T data);
|
2018-11-21 21:18:23 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Gets the pointer for virtual memory where the page is marked as RasterizerCachedMemory.
|
|
|
|
* This is used to access the memory where the page pointer is nullptr due to rasterizer cache.
|
|
|
|
* Since the cache only happens on linear heap or VRAM, we know the exact physical address and
|
|
|
|
* pointer of such virtual address
|
|
|
|
*/
|
2020-01-04 22:39:54 +00:00
|
|
|
MemoryRef GetPointerForRasterizerCache(VAddr addr);
|
2018-11-21 21:18:23 +00:00
|
|
|
|
2020-01-04 22:39:54 +00:00
|
|
|
void MapPages(PageTable& page_table, u32 base, u32 size, MemoryRef memory, PageType type);
|
2018-12-11 03:01:09 +00:00
|
|
|
|
2018-12-01 22:46:18 +00:00
|
|
|
class Impl;
|
2018-11-21 21:18:23 +00:00
|
|
|
|
2018-12-01 22:46:18 +00:00
|
|
|
std::unique_ptr<Impl> impl;
|
2019-08-07 01:53:56 +00:00
|
|
|
|
|
|
|
friend class boost::serialization::access;
|
2019-12-27 21:07:29 +00:00
|
|
|
template <class Archive>
|
|
|
|
void serialize(Archive& ar, const unsigned int file_version);
|
2020-01-04 22:39:54 +00:00
|
|
|
|
|
|
|
public:
|
|
|
|
template <Region R>
|
|
|
|
class BackingMemImpl;
|
2018-11-21 03:38:47 +00:00
|
|
|
};
|
|
|
|
|
2018-11-21 21:51:41 +00:00
|
|
|
/// Determines if the given VAddr is valid for the specified process.
|
|
|
|
bool IsValidVirtualAddress(const Kernel::Process& process, VAddr vaddr);
|
|
|
|
|
2017-07-22 02:17:57 +00:00
|
|
|
} // namespace Memory
|
2020-01-04 22:39:54 +00:00
|
|
|
|
|
|
|
BOOST_CLASS_EXPORT_KEY(Memory::MemorySystem::BackingMemImpl<Memory::Region::FCRAM>)
|
|
|
|
BOOST_CLASS_EXPORT_KEY(Memory::MemorySystem::BackingMemImpl<Memory::Region::VRAM>)
|
|
|
|
BOOST_CLASS_EXPORT_KEY(Memory::MemorySystem::BackingMemImpl<Memory::Region::DSP>)
|
|
|
|
BOOST_CLASS_EXPORT_KEY(Memory::MemorySystem::BackingMemImpl<Memory::Region::N3DS>)
|